LDT generates a complete and unambiguous specification for combinatorial and sequential logic. All transitions for all states and all input combinations are specified without mathematical relationships or equations. Because the specification is complete, certain analysis is possible, such as identification of dead and hanging states or an exhaustive search for worst and best case performance paths.
LDT is especially useful where system behavior must be proven correct, such as applications that are fault tolerant, data secure, or are subject to litigation. At the option of the operator, LDT can reduce logic and produce source files (c, Pascal, Ada, VHDL, espresso) with several implementations in hardware or software. LDT offers multiple views of the logic, several means of analysis and several interactive debuggers. With its higher degree of rigor and its increased visibility into the final design, LDT increases the chance of finding logic faults in the early, inexpensive design phase. The amount of rigor is user selected to meet system needs.
LDT is based upon a hierarchy of Karnaugh maps that relate input variables to next state and output variables. Known don’t care areas of the logic space are collapsed in order to manage its size. Logic can be minimized.
LDT has many user options, making it a valuable fit for a broad set of applications.