* ** ***ASSURANT DESIGN AUTOMATION, LLC*** **Technical Data Sheet*

The Logic Design Tool **LDT 4.1 **

**Assurant Design Automation’s Logic Design Tool (LDT)** **4.1** is a graphical aid for developing and analyzing digital control.

LDT increases the likelihood of exposing logical errors in the early requirements design phase. With LDT, all logical conditions and actions are displayed in a manner where they may be viewed, considered, specified, executed and analyzed before the logic is fielded. When the logic specification is complete, it can be automatically implemented in software or hardware source code, thus eliminating human error. LDT also displays the logic with multiple views and actions, so the designer has a greater chance to find a design error. It allows design work to be completed up front and as a whole – not piecemeal – and as such can save significant analysis, integration, test and rework time.

**User Selections**

**Specification Entry:**- Default, Single Entry, Transition Boolean, Output Bit Boolean.
- Next State Bit Boolean, Don’t Care, Test Vector, Truth Table, espresso.

**Alternate Views:**- Truth Table, If-Then-Else, Case, STD, Timing Diagrams, Boolean Equations, Karnaugh Map Patterns, Hierarchy.

**Analysis:**- Interactive Requirement Debugger, Dead, Hanging, No Decision States.
- Worst, Best Case Execution Paths, Logic Reduction Report.

**Transform Implementations:**- Boolean Equation, Software Array, If-then-else, Case.

**Reverse Engineer:**- VHDL, espresso.

**Unique Functions**

LDT Capabilities Not Found in Other Tools:

- Specify logic that is complete and unambiguous without the use of equations.
- Find the worst and best case execution time paths, accumulated time on given path, unseen sneak paths.
- Generate exhaustive set of test vectors for all paths.
- Easily show a transition from any state to many or all states.
- Display a large (greater than 16) number of states and transitions on a readable diagram without grouping sub-states.
- Find the minimal state machine implementation for speed/number of gates/reliability with a report of the rationale behind the reduction.
- Represent both combinatorial and sequential logic with same format.
- Executable specification at the Boolean equation level.

**Unique Views**

Multiple views increase the chance that a logical oversight will be exposed. For this reason, LDT offers:

- State machine interactive requirement test with animated inputs, outputs and sum of products.
- Display of all transitions from a given state with equation for each transition.
- Worst and best case execution paths, sneak paths.
- Karnaugh map patterns of logic with don’t care regions.
- Dead, hanging and no decision states report; entries and exits from each state.
- Conflict upon entry overlap, indication of not-yet-specified conditions.
- Collapse of don’t care logic space to reduce complexity.
- Comments in source code and documentation describing all transitions.

**Automatic Code/Document**

**Generation**

**Source Code Output**- C, Pascal, Ada, Assembly, VHDL, espresso.
- Source code verified for consistency by T-VEC requirements analysis.
- Exhaustive test vectors.

**Documentation Artifacts**- Specification Description, Notes
- Input To Output and State Bit Transform, Sum Of Products
- Finite State Machine Karnaugh Maps
- State
- Intermediate
- Transition

- Source code Files
- Ada
- Specification
- Body
- Interactive Driver
- Exhaustive Unit Test Driver

- VHDL
- C
- Driver
- Body

- Pascal

- Ada
- Espresso Formatted Truth Table
- State and Output Bit Model
- State Transition Analysis
- Logic Reduction Report
- Sum of Product Transform Metrics

The chance of exposing a logical error will increase with each additional model, analysis, report and metric.

**Future Capabilities**

Along with high assurance applications, LDT can easily be improved to perform the following functions:

**High Speed Logic Design**: Minimize hardware logic for speed, chip area size and component count.

**Reliability Calculation**: Compute total system probability of success based on combinations of line replaceable units needed for system success and their individual mean time between failures.

**Source Code Logic Analysis**: Examines existing code, analyzes and displays its logic structure in multiple LDT formats.

**Logic Tutorial**: Present a programmed learning tutorial sold via the web at cost to universities, technical schools and consortiums. This option will help undergraduates to be easily familiar with LDT and graduating students will leave as advocates for LDT’s utility.

**Hardware Synthesis:** Interface with a hardware design tool that finds the minimal solution for combinatorial, synchronous, asynchronous timelines.

**Minimal/Required System **

**Configuration**

OS Platforms |
Windows Me, 2000, XP, Vista, 8.0 |

Compilers |
Visual C++ 6.0, 7.0, 7.1Visual C++ 2005 and 2008R and R PC based Ada compilerDelphi 2007 CodeviewEspressoVHDL Simili 3.1Simple Solver 2.4.2 Hardware SynthesisT-VEC Requirement Error Analysis |

CPU processor |
2 GHz or faster |

RAM |
768 MB minimum1 Gb recommended |

Disk Space |
1 Gb minimum |

Peripherals |
CD-ROM drive for installation |

Display |
65000 colors, 17 inch recommended |